(1) Field of The Invention
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit utilizing a partially recessed shallow trench isolation (STI) scheme, in conjunction with a passivating silicon nitride trench liner, to fabricate borderless contacts.
In sub-micron technology shallow trench isolation (STI) has become a standard means of isolation for semiconductor devices and has replaced other isolation methods, i.e., LOCOS (Localized Oxidation of Silicon) which require more valuable area. In the conventional shallow trench isolation process, trenches are formed in a semiconductor substrate between electrically active areas, i.e., MOSFET gates and source/drains, and electrically isolate MOSFET's from each other. The trenches are filled with an insulating material, such as silicon oxide, to provide electrical insulation. Active devices, including MOSFET's, transistors and resistors are fabricated into the semiconductor substrate in the "active" regions with shallow trench isolation (STI), isolating the regions in between the active devices.
As transistor dimensions approached sub-micron, the conventional contact structures in use started to limit the device performance in several ways. First, it is difficult to minimize the contact resistance if the contact hole is also of minimum size and problems with cleaning small contact holes become a concern. In addition, with defined conventional contacts, the area of the source/drain regions cannot be minimized because the contact hole has be aligned to these regions with a separate masking step, and a large "extra" area has to be allocated for possible misalignment. Furthermore, this larger "extra" area also results in increased source/drain-to-substrate junction capacitance, which impacts device speed. Borderless contacts or "unframed" contacts solve many of the micron and sub-micron MOSFET contact problems, easing both the device ground rule designs and easing the processing problems associated with conventional "framed" contacts. The borderless contact makes better use of the space and area over the source/drain region, as will be described in more detail. Borderless contacts are part of the advanced designs and processing associated with shallow trench isolation (STI).
(2) Description of Related Art
With conventional shallow trench isolation (STI) processes, it is a problem to form a borderless contact over the trench region. The borderless contact or "unframed" contact is a contact which overlies and exposes both the active and isolation regions of the semiconductor substrate, usually for the purpose of making contact to a diffusion region formed in the substrate. One problem of forming borderless contacts in combination with conventional shallow trench isolation (STI) involves the etching of the contact hole opening through interlevel layers of dielectrics, while at the same time, trying to avoid etching the dielectric material in trench. Oftentimes, the dielectrics are types of silicon oxide, both for the interlevel and trench fill material. Therefore, the trench filled oxide can be etched and damaged due to the contact hole etch. If the trench isolation material is etched back along the wall of the trench, deleterious effects can occur, i.e., leakage and shorting at the edge of the P/N junction, especially when this region becomes filled with a conducting material.
U.S. Pat. No. 5,807,784 entitled "Device Isolation Methods for a Semiconductor Device" granted Sep. 15, 1998 to Kim describes a method of forming a device isolation layer in semiconductor device comprising of a two step method of forming field oxide in shallow trench isolation (STI). The first step consists of implanting oxygen ions into the bottom of trench in the field region of a semiconductor substrate, and oxidizing the oxygen implanted region to form a field oxide layer. The second step consists of depositing insulation material to further fill the trench.
U.S. Pat. No. 5,807,490 entitled "METHOD OF FILLING SHALLOW TRENCHES" granted Sep. 8, 1998 to Fiegl et al shows a method of isolation in silicon integrated circuit processing which overfills the trench by a fill margin and then deposits a temporary layer of polysilicon having a thickness less than the trench depth. A oxide layer is used as a polishing stop. The temporary layer is polished outside the trench, using a fill layer and polishing stop layer as polishing stops for chemical mechanical polish (CMP). The polishing stop layer is removed by CMP, together with the same thickness of fill layer and temporary polysilicon layer, resulting in surface planarity. The remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.
U.S. Pat. No. 5,817,568 entitled "Method of Forming a Trench Isolation Region" granted Oct. 6, 1998 to Chao describes a method, using multi-trench formation techniques, to define the respective depths of trenches having different widths. The method includes forming a buffer oxide layer and polishing stop layer, in sequence, above a semiconductor substrate. Then, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are defined to form at least one narrow trench. Thereafter, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are again defined to form at least one wide trench. Next, a portion of the oxide layer and a portion of the polishing stop layer are removed to form a planarized surface. Finally, the polishing stop layer and the buffer oxide layer are removed.
U.S. Pat. No. 5,652,176 entitled "Method for Providing Trench Isolation and Borderless Contact" granted Jul. 29, 1997 to Maniar et al describes a method of trench isolation which uses a trench liner comprised of aluminum nitride. Another similar patent is U.S. Pat. No. 5,677,231 entitled "Method for Providing Trench Isolation" granted Oct. 14, 1997 to Maniar et al also shows shallow trench isolation (STI) and a borderless contact process with an aluminum nitride liner under the STI silicon oxide. During the formation of the contact opening, using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at the corner of the trench. By protecting the junction, subsequent formation of a conductive plug will not electrically short circuit the junction, and keeps diode leakage low.
U.S. Pat. No. 5,268,330 entitled "Process for Improving Shee Resistance of an Integrated Circuit Device Gate" granted Dec. 7, 1993 to Givens et al describes a process involving shallow trench isolation (STI) and contact above P-N junctions that can be made to be borderless contacts. A passivating layer is deposited over an integrated circuit device, fabricated using silicidation. An insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of passivating layer above the gate is removed. A trench above the junctions is formed by removing insulation and using the passivating layer as an etch stop. Then a portion of the passivating layer is removed above the junction. The gate can be further silicided and opening above the gate and trench can be filled. The contacts above the junction can be borderless contacts.
The present invention is directed to a novel method of using CMP to selectively remove a second material over a first material and produce a planar first material surface, free of second material residue. The method of the present invention requires less CMP processing time, has lower cost than conventional CMP methods and produces a polished surface having superior planarity.